By Cicero S. Vaucher
This article describes a conceptual framework for studying the functionality of PLL frequency synthesizers, and offers optimization strategies for different functionality features. It comprises uncomplicated details and in-depth wisdom, generally illustrated with useful layout examples utilized in business items.
Read or Download Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science) PDF
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Additional resources for Architectures for RF Frequency Synthesizers (The Springer International Series in Engineering and Computer Science)
4 The Phase-Frequency Detector/Charge-Pump Combination The block diagram of a common implementation of the phase-frequency detector is presented in Figure 3-2. It consists of two D-type flip-flops (D-FF) which have their D inputs connected to the active level. There are many circuit implementations of a PFD which provide the same functionality [1,5,7,8]. The main advantage of the D-FF based implementation is its compactness. The upper D-FF, which is clocked by generates the up signal. The lower D-FF, clocked by generates the down signal.
When the loop is locked the phase of the divided output signal accurately tracks the phase of the reference signal The phase-lock process forces the frequencies of and to be equal. 1 Voltage-Controlled Oscillators The voltage-controlled oscillator (VCO) generates the output signal of the PLL. The frequency of the VCO signal is dependent on the voltage at its tuning input. The relationship between the output frequency and the tuning voltage can be written as where is the VCO gain factor in [Hz/V] and is the output frequency when the tuning voltage is 0 Volt.
With this situation, stepping the frequency of the synthesizer changes the received channel. Other applications require a minimum step size smaller than the channel width, for example, to implement automatic frequency control (AFC) functions. An undesired frequency offset can be detected between the frequency of the receiver input signal and the frequency generated by the synthesizer. The Settling Time 13 offset can be then decreased by generation of an output frequency which has a smaller offset with respect to the input frequency.